Performance Analysis of Parallel Prefix Adder Based on FPGA

Parallel-prefix structures (also known as carry tree) are found to be common in high performance adders in very large scale integration (VLSI) designs because of the delay is logarithmically proportional to the adder width. Such structures can usually be classified into three basic stages which are precomputation, prefix tree and post-computation. However, this performance advantage does not translate directly into FPGA implementations due to constraints on logic block configurations and routing overhead. Three types of carry-tree adders (the KoggeStone, Brent Kung, Han Carlson and Harris adder) in this paper investigates and compares them to the simple Ripple Carry Adder (RCA.).These implementations have been successfully done in verilog hardware descriptive language using Xilinx Integrated Software Environment (ISE) 13.2 design suit. These designs are implemented in Xilinx Spartan 6 ,Spartan 6 low power, virtex 6, virtex 6 low power Field Programmable Gate Arrays (FPGA) and delays are measured using xpower analyser 13.2 and all these adder’s Comparison of Slice utilization, No. of logic levels required & Delay are investigated and compared finally. Keywords— parallel prefix adders; carry tree adders; FPGA; logic analyzer; delay; power.